1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a method of accessing a dynamic Random Access Memory (dRAM) in which dynamic memory cells for individual cell access are integrated, and a dRAM system.
2. Description of the Related Art
A conventional semiconductor memory device is generally operated in response to a control signal from an external Central Processing Unit (CPU). In the dRAM, an upper address designation signal, a lower address designation signal, row address strobe RAS, column address strobe CAS, write trigger signal WE, and the like are used. These control signals must be input from the external CPU or the like at a voltage, an order, and a timing which are prescribed by specifications of the semiconductor memory device so as to properly operate the semiconductor memory device.
The row address strobe (to be referred to as an RAS hereinafter) is a signal for selecting a mode which designates a row of the semiconductor memory device, and a column address strobe (to be referred to as a CAS hereinafter) is a signal for selecting a mode which designates a column of the semiconductor memory device. In both the read and write modes, signals RAS and CAS are always input in the order named.